Christopher W. Fletcher

Chip Tapeout

Chip thumbnail In March 2015, in a collaboration with David Wentzlaff's group at Princeton, we taped out a 25 core Ascend (aka Piton) processor in a 32nm process. Click the picture to get a blowup. The ORAM controller came out to about 1mm^2. For the final layout, we were very conservative at the top level, so the 'real' area is somewhere between .5-1mm^2.

Bring-up: The ORAM successfully passed its self tests on bring-up! The ORAM runs at 857 MHz, dissipating 166 mW @ 1.1V! To verify functionality, we have a traffic generator on the chip that simulates a last level cache miss pattern and supplies the ORAM with requests. The ORAM/chip then talks to a Spartan6 FPGA which is connected over UART to a laptop. The UART/laptop simulates a memory substrate such as DRAM. For power measurements, we have a mode where the ORAM loops data back on itself (thus, 166 mW doesn't include the back-end I/O (e.g., DRAM) controller--it is made up of the logic and SRAM power in the ORAM core itself). See here for a chip selfie. See here for the transcript of the first 2 accesses ("received from chip..." is ciphertext received from the ORAM).

A paper describing the design can be found here. The ORAM controller RTL is open source here.