Christopher W. Fletcher
Project year: Fall, 2008
Partners: Ilia Lebedev, Alex Williams
Updated: August 1, 2009

FLINT (Flexible Latency-Insensitive SPARC) is a SPARCv8 processor implementation optimized for Virtex5 FPGAs. FLINT was developed during Fall 2008 and will feature support for all integer-unit SPARCv8 instructions and all SPARCv8 traps. Forgoing RAW hazard architectural optimizations, FLINT features a state-based handshaking scheme between components that allows each component to take a variable number of cycles to complete a task. For portability, the memory backend interface is also tolerant of variable latencies. This allows FLINT to be connected to on-chip memory such as block or distributed memory, or off-chip memory such as DDR2RAM.

FLINT was developed using primarily Verilog, Java and ANT. Java was used to create a SPARCv8 functional simulator and to coordinate a medium-independent bit-banging framework for communicating with a FLINT implementation deployed on an FPGA. ANT was used to build FLINT from source and to automate a comprehensive test suite that is matched against the functional simulator. See ANTEDA for more information about the ANT libraries used.

FLINT is still no longer in active development. All code/technologies that were developed in-house are BSD licensed, however, so if you are interested in obtaining source: contact me.


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