Christopher W. Fletcher

High-{T, P} Reconfigurable Architectures

Project year: Summer, 2010 - Fall, 2010
Partners: Ilia Lebedev, Narges Bani Asadi
Updated: October 22, 2010

In the summer after I graduated from U.C. Berkeley, I was a part of two related projects that both asked a similar question: "how well can reconfigurable devices (such as FPGAs) implement more traditional HPC/throughput architectures?"

The first project, for which I was a research assistant, was titled "MARC: A Many-Core Approach to Reconfigurable Computing." The idea here is that a good way to design to FPGAs is to think of the FPGA fabric as a micro-architectural template, which you can customize on a per-application basis. For this project, we ported a Systems Biology kernel that I had worked on previously to a MARC template and compared its performance against the hand-custom version that I designed.

The second project, for which I was team leader, was titled "Bridging the GPGPU-FPGA Efficiency Gap." While in Italy (July), I reformulated another Systems Biology kernel in order to minimize its off-chip memory footprint. This was desirable because the FPGA's 'off-chip byte:OP' ratio was very low (the FPGAs we were using at the time had a 3.7 Tb/s on-chip BRAM bandwidth and only a ~50 Gb/s off-chip bandwidth). Coincidentally, the transformation made the FPGA design's execution model and architecture look very similar to that of a GPGPU. We took this as an opportunity to compare the two platforms head to head, where the big question was "can an FPGA make a better GPGPU than a GPGPU." (I've posted the first draft of my notes on the FPGA's architecture here).