Christopher W. Fletcher
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Research


I am a computer architect with broad interests in security (from applied cryptography to hardware-based attacks and defenses) and domain-specific acceleration. Here is my CV and Google scholar profile.

My group and I are fortunate to maintain multiple collaborations with both Intel and NVIDIA on these topics. In particular, I lead a multi-university Intel Strategic Research Alliance (ISRA) center to study microarchitectural side channels (year 1 retreat group photo).

Navigation:
  1. Select papers
  2. Select project
  3. Peer-reviewed papers
  4. Patents
  5. Theses
  6. Misc. papers (e.g., eprints)
  7. Academic blogs
  8. Selected press
  9. Talks
  10. Posters
  11. Funding
  12. Tutorials/Misc. Resources

Select Papers


Here are a few representative projects:

  1. Data Oblivious ISA Extensions for Side Channel-Resistant and High Performance Computing

    Introduces ISA-level principles for writing noninterferent programs on modern out-of-order, speculative machines. The key idea is that by specifying security goals explicitly but abstractly (in a microarchitecture-independent fashion), software writers are not burdoned with low-level hardware details (i.e., can write portable code), and hardware designers are once again free to implement hardware optimizations, just subject to the constraint that the security policy isn't violated. (Paper link is the extended version, which is also a bit sharper than the conference version.) See RISC-V BOOM prototype here.

  2. Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data

    Introduces new mechanisms and abstractions for blocking and reasoning about speculative execution attacks. The premise is that speculative execution is safe unless a "sensitive value" reaches a "covert channel". This idea was inspired from "Confidential ⇏ Unsafe Instruction" in the Data Oblivious ISA paper, which itself shares DNA with the policy "High ⇏ Low" from information flow. The paper's technical meat is to define new notions of what is a "sensitive value" and to define a new abstraction through which to reason about "covert channels", and speculative execution attacks more generally, on modern processors. See formal analysis/security proof here.

  3. MicroScope: Enabling Microarchitectural Replay Attacks

    Introduces microarchitectural replay attacks, a novel class of processor vulnerability based around the premise that on modern out-of-order machines, a single logical dynamic instruction may execute more than once. This can be leveraged by attackers to create new privacy- and integrity-breaking attacks. The paper demonstrates a proof-of-concept microarchitectural replay attack in the SGX setting that de-noises an extremely noisy microarchitectural side channel---port contention---in a single run of the victim application. See release of the Microscope framework here.

  4. UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition

    Introduces the pigeonhole principle for DNNs: as weight precision drops, the same weight value is bound to repeat within and across filters many times. To exploit these weight repetitions, we introduce the activation group reuse (AGR) algorithm, which reduces the number of multiplications, additions and memory lookups needed to perform DNN inference, while simultaneously compressing the DNN model to a level competitive with state-of-the-art quantization schemes. Finally, we build an AGR-enabled accelerator which reduces DNN inference energy consumption by up to 4x.

  5. ExTensor: An Accelerator for Sparse Tensor Algebra

    Introduces a new paradigm for orchestrating sparse tensor computation, embodied in a concrete accelerator called ExTensor. In an ExTensor-like accelerator, tensors are encoded in a hierarchical compressed representation to enable tiling in a multi-level memory hierarchy, and storage savings resulting from sparsity. Then, during computation, those tensors are "hierarchically intersected" at each level of the memory hierarchy to eliminate ineffectual metadata/data fetches and compute. To visualize hierarchical intersection, consider the axiom x * 0 = 0. In high-dimensional tensor algebra, x may be a scalar, tile/tensor, loopnest, etc. ExTensor's hierarchical intersection allows us to identify these cases and skip work related to x for different types of x.

During my PhD, my focus was Architecture + Security, and our work spanned taping out a secure processor to designing asymptotically better cryptography. Here are two representative papers:

  1. Onion ORAM: A Constant Bandwidth Blowup Oblivious RAM

    Introduces the first Oblivious RAM with constant bandwidth blowup, based on standard cryptographic assumptions. The key techniques are to use homomorphic encryption to "break" the Goldreich-Ostrovsky lower bound, and to develop a new "bounded feedback ORAM" to make the ORAM protocol's circuit depth logarithmic in the database size instead of polynomial.

  2. Design and Implementation of the Ascend Secure Processor

    This paper consolidates ideas from multiple other papers (ASPLOS'15, FCCM'15), related to our efforts in taping out the first ORAM in silicon, and presents post-silicon power numbers for the ORAM controller once we powered it up in the lab. It also more holistically covers the execution model for Ascend (which originally appeared in STC'12).

Also, here is a 1-pager on the Ascend project that expounds my philosophy in secure hardware design.

Select Project

Chip thumbnail
In March 2015, in a collaboration with David Wentzlaff's group at Princeton, we taped out a 25 core Ascend (aka Piton) processor in a 32nm process. Click the picture to get a blowup. The ORAM controller came out to about 1mm^2. For the final layout, we were very conservative at the top level, so the 'real' area is somewhere between .5-1mm^2.

Bring-up: The ORAM successfully passed its self tests on bring-up! The ORAM runs at 857 MHz, dissipating 166 mW @ 1.1V! To verify functionality, we have a traffic generator on the chip that simulates a last level cache miss pattern and supplies the ORAM with requests. The ORAM/chip then talks to a Spartan6 FPGA which is connected over UART to a laptop. The UART/laptop simulates a memory substrate such as DRAM. For power measurements, we have a mode where the ORAM loops data back on itself (thus, 166 mW doesn't include the back-end I/O (e.g., DRAM) controller--it is made up of the logic and SRAM power in the ORAM core itself). See here for a chip selfie. See here for the transcript of the first 2 accesses ("received from chip..." is ciphertext received from the ORAM).

A paper describing the design can be found here. The ORAM controller RTL is open source here.

Peer-Reviewed Papers


Color code: Blue: conference, Green: journal, Purple: workshop.

Top architecture conferences: ASPLOS, HPCA, ISCA, MICRO
Top security conferences: CCS, NDSS, Oakland/SP, USENIX Security

  1. Game of Threads: Enabling Asynchronous Poisoning Attacks; Jose Rodrigo Sanchez Vicarte, Ben Schreiber, Riccardo Paccagnella, Christopher W. Fletcher; ASPLOS, 2020

  2. The Security Pitfalls of Memory Hierarchy Compression: New Side Channels and Attacks on Compressed Caches; Po-An Tsai, Andres Sanchez, Christopher W. Fletcher, Daniel Sanchez; ASPLOS, 2020

  3. Cache Telepathy: Leveraging Shared Resource Attacks to Learn DNN Architectures; Mengjia Yan, Christopher Fletcher, Josep Torrellas; USENIX Security, 2020

  4. ExTensor: An Accelerator for Sparse Tensor Algebra; Kartik Hegde, Hadi Asghari-Moghaddam, Michael Pellauer, Neal Crago, Aamer Jaleel, Edgar Solomonik, Joel Emer, Christopher W. Fletcher; MICRO, 2019

  5. Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data; Jiyong Yu, Mengjia Yan, Artem Khyzha, Adam Morrison, Josep Torrellas, Christopher W. Fletcher; MICRO, 2019
    Best Paper Award
    Formal analysis/security proof: here

  6. A Retrospective on Path ORAM; Emil Stefanov, Marten van Dijk, Elaine Shi, Christopher W. Fletcher, Ling Ren, Xiangyao Yu, Srinivas Devadas; IEEE TCAD, 2019

  7. Approximate Checkers; Abdulrahman Mahmoud, Paul Reckamp, Panqiu Tang, Christopher W. Fletcher, Sarita V. Adve; WAX, 2019

  8. MicroScope: Enabling Microarchitectural Replay Attacks; Dimitrios Skarlatos, Mengjia Yan, Bhargava Gopireddy, Read Sprabery, Josep Torrellas, Christopher W. Fletcher; ISCA, 2019
    Open source release here
    Highest ranked paper in double-blind review process

  9. SecDir: Secure Directories to Defeat Directory Side Channel Attacks; Mengjia Yan, Jen-Yang Wen, Christopher W. Fletcher, Josep Torrellas; ISCA, 2019

  10. gem5-Approxilyzer: an Open Source Tool for Application-level Soft Error Analysis; Radha Venkatagiri, Khalique Ahmed, Abdulrahman Mahmoud, Sasa Misailovic, Darko Marinov, Christopher W. Fletcher, and Sarita V. Adve; DSN, 2019
    Open source release here

  11. Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration; Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal Crago, Kartik Hegde, Rangarajan Venkatesan, Stephen W. Keckler, Christopher W. Fletcher, Joel Emer; ASPLOS, 2019
    Open source release here

  12. Minotaur: Adapting Software Testing Techniques for Hardware Errors; Abdulrahman Mahmoud, Radha Venkatagiri, Khalique Ahmed, Sasa Misailovic, Darko Marinov, Christopher W. Fletcher, Sarita V. Adve; ASPLOS, 2019

  13. Data Oblivious ISA Extensions for Side Channel-Resistant and High Performance Computing; Jiyong Yu, Lucas Hsiung, Mohamad El Hajj, Christopher W. Fletcher; NDSS, 2019
    Open source release here
    Distinguished Paper Finalist
    Finalist, CSAW Applied Research Competition 2019

  14. Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World; Mengjia Yan, Read Sprabery, Bhargava Gopireddy, Christopher W. Fletcher, Roy Campbell, Josep Torrellas; Oakland/SP, 2019

  15. InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy; Mengjia Yan, Jiho Choi, Dimitrios Skarlatos, Adam Morrison, Christopher W. Fletcher, Josep Torrellas; MICRO, 2018
    Open source release here
    IEEE Micro's Top Picks 2019 Honorable Mention

  16. Morph: Flexible Acceleration for 3D CNN-based Video Understanding; Kartik Hegde, Rohit Agrawal, Yulun Yao, Christopher W. Fletcher; MICRO, 2018

  17. UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition; Kartik Hegde, Jiyong Yu, Rohit Agrawal, Mengjia Yan, Michael Pellauer, Christopher W. Fletcher; ISCA, 2018

  18. Path ORAM: An Extremely Simple Oblivious RAM Protocol; Emil Stefanov, Marten van Dijk, Elaine Shi, T-H Hubert Chan, Christopher W. Fletcher, Ling Ren, Xiangyao Yu, Srinivas Devadas; JACM, 2018

  19. ZeroTrace: Oblivious Memory Primitives from Intel SGX; Sajin Sasy, Sergey Gorbunov, Christopher W. Fletcher; NDSS, 2018
    Open source release here

  20. Design and Implementation of the Ascend Secure Processor; Ling Ren, Christopher W. Fletcher, Albert Kwon; Marten van Dijk; Srinivas Devadas; IEEE TDSC, 2017

  21. Asymptotically tight bounds for composing ORAM with PIR; Kartik Nayak, Ling Ren, Christopher W. Fletcher, Ittai Abraham, Benny Pinkas; PKC, 2017

  22. HOP: Hardware makes Obfuscation Practical; Kartik Nayak, Christopher W. Fletcher, Ling Ren, Nishanth Chandran, Satya Lokam, Elaine Shi, Vipul Goyal; NDSS, 2017
    Open source release here

  23. Onion ORAM: A Constant Bandwidth Blowup Oblivious RAM; Srinivas Devadas, Marten van Dijk, Christopher W. Fletcher, Ling Ren, Elaine Shi, Daniel Wichs; TCC, 2016; (Alphabetical authors, L. Ren and I shared lead author)

  24. Constants Count: Practical Improvements to Oblivious RAM; Ling Ren, Christopher W. Fletcher, Albert Kwon, Emil Stefanov, Elaine Shi, Marten van Dijk, Srinivas Devadas; USENIX Security, 2015

  25. PrORAM: Dynamic Prefetcher for Oblivious RAM; Xiangyao Yu, Syed Kamran Haider, Ling Ren, Christopher W. Fletcher, Albert Kwon, Marten van Dijk, Srinivas Devadas; ISCA, 2015

  26. A Low-Latency, Low-Area Hardware Oblivious RAM Controller; Christopher W. Fletcher, Ling Ren, Albert Kwon, Marten van Dijk, Emil Stefanov, Dimitrios Serpanos, Srinivas Devadas; FCCM, 2015

  27. Freecursive ORAM: [Nearly] Free Recursion and Integrity Verification for Position-based Oblivious RAM; Christopher W. Fletcher, Ling Ren, Albert Kwon, Marten van Dijk, Srinivas Devadas; ASPLOS, 2015
    Open source release here

  28. Suppressing the Oblivious RAM Timing Channel While Making Information Leakage and Program Efficiency Trade-offs; Christopher W. Fletcher, Ling Ren, Xiangyao Yu, Marten van Dijk, Omer Khan, Srinivas Devadas; HPCA, 2014

  29. Path ORAM: An Extremely Simple Oblivious RAM Protocol; Emil Stefanov, Marten van Dijk, Elaine Shi, Christopher W. Fletcher, Ling Ren, Xiangyao Yu, Srinivas Devadas; CCS, 2013
    Best Student Paper Award
    Top Picks in Hardware & Embedded Security 2018

  30. Generalized External Interaction with Tamper-Resistant Hardware with Bounded Information Leakage; Xiangyao Yu, Christopher W. Fletcher, Ling Ren, Marten van Dijk, Srinivas Devadas; CCSW, 2013

  31. A Framework to Accelerate Sequential Programs on Homogeneous Multicores; Christopher W. Fletcher, Rachael Harding, Omer Khan, Srinivas Devadas; VLSI SoC, 2013

  32. Integrity Verification for Path Oblivious-RAM; Ling Ren, Christopher W. Fletcher, Xiangyao Yu, Marten van Dijk, Srinivas Devadas; HPEC, 2013

  33. Design Space Exploration and Optimization of Path Oblivious RAM in Secure Processors; Ling Ren, Xiangyao Yu, Christopher W. Fletcher, Marten van Dijk, Srinivas Devadas; ISCA, 2013

  34. Towards an Interpreter for Efficient Encrypted Computation; Christopher W. Fletcher, Marten van Dijk, Srinivas Devadas; CCSW, 2012

  35. A Secure Processor Architecture for Encrypted Computation on Untrusted Programs; Christopher W. Fletcher, Marten van Dijk, Srinivas Devadas; STC, 2012

  36. HORNET: a cycle-level multicore simulator; Pengju Ren, Mieszko Lis, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Nanning Zheng, Srinivas Devadas; IEEE TCAD, Vol. 31, No. 6, June 2012

  37. A Low-overhead Dynamic Optimization Framework on Multicores; Christopher W. Fletcher, Rachael Harding, Omer Khan, Srinivas Devadas; PACT (short paper), 2012

  38. Exploring Many-core Design Templates for FPGAs and ASICs; Ilia Lebedev, Christopher W. Fletcher, Shaoyi Cheng, James Martin, Austin Doupnik, Daniel Burke, Mingjie Lin, John Wawrzynek; IJRC, Article ID 439141, Volume 2012

  39. Scalable Accurate Multicore Simulation in the 1000 core era; Mieszko Lis, Pengju Ren, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Srinivas Devadas; ISPASS, 2011

  40. Brief Announcement: Distributed Shared Memory based on Computation Migration; Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Christopher W. Fletcher, Michel Kinsy, Ilia Lebedev, Omer Khan, Srinivas Devadas; SPAA (short paper), 2011

  41. Bridging the GPGPU-FPGA Efficiency Gap; Christopher W. Fletcher, Ilia Lebedev, Narges B. Asadi, Daniel R. Burke, John Wawrzynek; ISFPGA (short paper), 2011

  42. MARC: A Many-Core Approach to Reconfigurable Computing; Ilia Lebedev, Shaoyi Cheng, Austin Doupnik, James Martin, Christopher W. Fletcher, Daniel Burke, Mingjie Lin, John Wawrzynek; ReConFig, 2010

  43. ParaLearn: A Massively Parallel, Scalable System for Learning Interaction Networks on FPGAs; Narges B. Asadi, Christopher W. Fletcher, Greg Gibeling, Karen Sachs, Eric Glass, Daniel Burke, Zoey Zhou, John Wawrzynek, Wing H. Wong, Garry P. Nolan; ICS, 2010; (N. Asadi and I shared lead author)
    Best Student Paper Award

Patents


  1. Technique for secure computation; Srinivas Devadas, Christopher W. Fletcher, Marten Van Dijk; Patent No. 8909967. (Note: there is currently a bug where only Marten is listed as inventor. The lawyers are fixing it...)

Theses


  1. Oblivious RAM: From Theory to Practice; Christopher W. Fletcher; Ph.D. Thesis; [Thesis]
    George M. Sprowls Award for outstanding Ph.D. thesis in CS at MIT

  2. Ascend: An Architecture for Performing Secure Computation on Encrypted Data; Christopher W. Fletcher; S.M. Thesis; [CSG Technical Memo 508]

Other Tech Reports/Articles


  1. Speculative Taint Tracking (STT): A Formal Analysis; Jiyong Yu, Mengjia Yan, Artem Khyzha, Adam Morrison, Josep Torrellas, Christopher W. Fletcher; Technical report

  2. Cache telepathy: Leveraging shared resource attacks to learn DNN architectures; Mengjia Yan, Christopher W. Fletcher, Josep Torrellas; arXiv preprint arXiv:1808.04761

  3. Bucket ORAM: Single Online Roundtrip, Constant Bandwidth Oblivious RAM; Christopher W. Fletcher, Muhammad Naveed, Ling Ren, Elaine Shi, Emil Stefanov; Cryptology ePrint Archive (IACR), Report 2015/1065, 2015. http://eprint.iacr.org/

  4. [Author Retrospective] AEGIS: Architecture for Tamper-Evident and Tamper-Resistant Processing; G. Edward Suh, Christopher W. Fletcher, Dwaine Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas; 25 Years of the International Conference on Supercomputing, 2014.

  5. Let's Stop Trusting Software With Our Sensitive Data; Christopher W. Fletcher, Marten van Dijk, Srinivas Devadas; IEEE Design and Test of ICs, March/April 2013. The Last Byte.

Academic Blogging


  1. Approaches to System Security: Using Cryptographic Techniques to Minimize Trust; Sigarch blog [article]; with Simha Sethumadhavan.

Selected Press


  1. Cybersecurity Factory nurtures early-stage startups in a tough field; Fortune [article]

  2. The Quest to Rescue Security Research From the Ivory Tower; Wired [article]

  3. Cloud security reaches silicon; MIT News [article]

  4. Hardware Trick Could Keep Cloud Data Safe; IEEE Spectrum [article]

  5. Devadas hardware disguises cloud servers memory-access patterns thwarting timing attacks; CSAIL News [article]

  6. Protecting data in the cloud; MIT News [article]

  7. A New Type of Security Chip Guards Against Big Data Snooping; Scientific American, Ascend has been named a "World Changing Idea"! [article]

Talks (ordered by project, then time)


  1. UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition; Facebook Research, 7/24/2019

  2. Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data
    1. Intel SCAP Yearly Meeting, 6/11/2019
    2. Open Source Enclaves Workshop, Berkeley CA, 7/25/2019

  3. MicroScope: Enabling Microarchitectural Replay Attacks; Intel Research Bi-Weekly SCAP Seminar Series, 5/14/2019

  4. Hardware Abstractions and Efficient Intersection for Tensor Algebra;
    1. Workshop on Compiler Techniques for Sparse Tensor Algebra, 1/26/2019
    2. DARPA SDH Open Session, 5/6/2019
    3. Facebook Research, 7/24/2019

  5. Data Oblivious Programming and Data Oblivious ISAs
    1. Open Source Enclaves Workshop, Berkeley CA, 8/29/2018
    2. International Workshop on Blockchain/Crypto Winterschool, Xi'an China, 12/10/2018
    3. Intel Research Bi-Weekly SCAP Seminar Series, 1/22/2019
    4. Intel SCAP Yearly Meeting, 6/11/2019
    [slides]

  6. Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World; AMD Weekly Seminar Series, 7/13/2018
    [slides]

  7. Systems-centric aspects in Holistic Defense against Information Leakage; Plenary talk, NSF Workshop on Side and Covert Channels in Computing Systems, Washington D.C., 3/22/2018
    [slides]

  8. Cryptography Can Outmaneuver Hardware; Hardware Security Workshop at Columbia University, New York City, 8/31/2016

  9. The Ascend Secure Processor: Concept to Silicon Implementation
    1. University of Illinois at Urbana-Champaign, 2/15/2016
    2. Stanford University, 2/23/2016
    3. Harvard University, 3/6/2016
    4. University of California--San Diego, 4/25/2016
    5. Nvidia Research, 7/14/2016

    I also gave subsets of this talk at:
    1. CHASE Conference (Conference on Secure/Trustworthy Systems and Supply Chain Assurance), University of Connecticut, 6/1/2016
    2. DIMACS Workshop (Center for Discrete Mathematics and Theoretical Computer Science), MIT, 6/11/2016

  10. Constants Count: Practical Improvements to Oblivious RAM; "ORAMorama" Technical Session at the 24th Usenix Security Symposium, Washington D.C., 8/13/2015
    [slides]

  11. Tiny ORAM: A Low-Latency, Low-Area Hardware Oblivious RAM Controller; "Implementation I" Technical Session at the 23rd IEEE Intl. Sym. on Field-Programmable Custom Computing Machines, Vancouver, Canada, 5/2/2015
    [slides]

  12. Onion ORAM: Constant Bandwidth ORAM using Additively Homomorphic Encryption;
    1. ORAM Day at Boston University, Boston, Massachusetts, 1/30/2015
    2. Charles River Crypto Day at Northeastern University, Boston, Massachusetts, 4/17/2015
    3. UBC Seminar, Vancouver, Canada, 5/3/2015
    4. ORAM Technical Session at the 13th Theory of Cryptography Conference, 1/13/2016
    [slides, shorter slides (with whole talk written out in comments section)]

  13. Hardware Security in Cloud Computing
    Presented at the Annual CSAIL Alliance Program meeting, Cambridge, 4/30/2014

  14. Suppressing the Oblivious RAM Timing Channel While Making Information Leakage and Program Efficiency Trade-offs; "Security and Cloning" Technical Session at the 20th Intl. Sym. on High Performance Computer Architecture, Orlando, Florida, 2/18/2014
    [slides]

  15. Techniques for Performing Secure Computation on Encrypted Data
    Presented at:
    1. the NSA-CSAIL visit, Cambridge, Massachusetts, 9/19/2012
    2. the MIT CSAIL security seminar series, Cambridge, Massachusetts, 10/1/2012
    3. 7th ACM Workshop on Scalable Trusted Computing (STC), Raleigh, North Carolina, 10/15/2012 (second half)
    4. 4th ACM Cloud Computing Security Workshop (CCSW), Raleigh, North Carolina, 10/19/2012 (first half)
    5. the Northrop Grumman-CSAIL visit, Cambridge, Massachusetts, 10/25/2012
    6. the Boston University security (BUSec) seminar series, Cambridge, Massachusetts, 12/10/2012
    7. MIT Lincoln Laboratory, Lexington, Massachusetts, 2/4/2013
    [slides]

  16. Bridging the GPGPU-FPGA Effciency Gap; "FPGA Architectures and Technology" Technical Session at the 19th Intl. Sym. on FPGAs, Monterey, California, 2/28/2011
    [slides]

  17. ParaLearn: A massively parallel, scalable system for learning interaction networks on FPGAs; "Applications" Technical Session at the 24th Intl. Conf. on Supercomputing, Tsukuba, Japan, 6/2/2010
    [slides]

    18. The slides for the below talks were subsumed by the ICS'10 and FPGA'11 talks:

  18. Scalable Bayesian Network Discovery with Reconfigurable Hardware
    Presented at:
    1. the BWRC Winter Retreat, Lake Tahoe, 1/10/2010
    2. the RAMP Winter Retreat, U.C. Santa Cruz, 1/28/2010

  19. Reconfigurable Computing & Bayesian Networks
    Presented at the GSRC Annual Research Symposium, San Jose, 9/3/2009

  20. Introduction to GateLib & MCMC on the BEE3
    Presented at the Nolan Lab "All Hands Meeting," Stanford, 6/15/2009

Posters


(Has not been updated since 2013.)

  1. Ascend: An Architecture for Performing Secure Computation on Encrypted Data; Presented at the ACSC Annual Conference, Boston, 11/12/2013 (and numerous other places ...)
    [poster]
    Best Poster Presentation Award, Second Place

  2. A Low-overhead Dynamic Optimization Framework on Multicores;
    Presented at:
    1. International Conference on Very Large Scale Integration, Istanbul, 10/6/2013
    2. the 21st IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques, Minneapolis, 9/20/2012
    [poster]

  3. Bridging the GPGPU-FPGA Efficiency Gap; Presented at the 19th International Symposium on Field-Programmable Gate Arrays, Monterey, 2/28/2011
    [poster]

  4. Scalable FPGA Solutions for Learning Bayesian Networks
    Presented at:
    1. the BWRC Winter Retreat, Lake Tahoe, 1/10/2010
    2. the BWRC Summer Retreat, U.C. Berkeley, 6/6/2010 (with an updated results pane)
    [poster]

  5. Curing Cancer with RCBIOS; Presented at the RAMP Summer Retreat, U. T. Austin, 6/23/2009
    [poster]

  6. flint; Presented at the RAMP Winter Retreat, U.C. Berkeley, 1/10/2009
    [poster]

Funding


* All funding amounts are my personal take/total grant budget.

  1. NSF CNS #1909999 (2019-2022); 500K, Lead PI
  2. Intel ISRA (2018-2021); 300K/1.5M (awarded as gift), Lead PI
  3. NSF CNS #1816226 (2018-2021); 250K/500K, Lead PI
  4. DARPA SDH #HR0011-18-3-0007 (2018-2022); 466K/23M, subcontractor under NVIDIA
  5. NSF CCF #1725734 (2017-2020); 250K/500K, Co PI
  6. Too many travel grants to list...

We thank NSF, DARPA/NVIDIA and Intel for their generous support!

Tutorials/Misc. Resources


  1. Crypto-hardware-software bibliography
  2. Tutorial on microarchitectural side/covert channels: ISCA'19

© Chris Fletcher 2019