Christopher W. Fletcher
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Research


I am a computer architect with broad interests in adjacent areas. Recently, a lot of my work has been related to security (from applied cryptography to hardware-based attacks and defenses) and domain-specific acceleration (from algorithm to hardware design). Here is my CV and Google scholar profile.

My group and I are fortunate to maintain multiple collaborations with both Intel and NVIDIA on these topics. In particular, I lead a multi-university Intel Strategic Research Alliance (ISRA) center to study processor security (year 1 retreat group photo).

A major goal in my research is to build efficient hardware systems that enforce security properties. One recent project was Data-Oblivious ISAs (OISAs) (shorter version), which facilitate whole-program security by composing the program into "locally secure" instructions. Check out our OISA prototype on the RISC-V BOOM processor. We extended this idea and built a data-oblivious runtime, enabling secure execution of code written in high-level interpreted languages like R. Follow-on work Speculative Taint Tracking (STT) (shorter version) optimizes the mechanism in OISA to comprehensively protect speculatively accessed data only, and introduces a new abstraction through which to think about microarchitectural leakage channels. Also see our security analysis and optimization framework for STT.

In the spirit of designing stronger TEE abstractions (not implementations), one of our recent projects focused on how to break security by attacking TEE abstractions (not implementations). In the course of the project we discovered microarchitectural replay attacks (shorter version), which show how to turn nearly arbitrary non-repeating code into repeating code, enabling new classes of privacy- and integrity-breaking attacks (e.g., de-noising nearly any uarch side channel, biasing TRNGs, ...). We released a kernel module that automates these attacks called Microscope. This project also led to asynchronous poisoning attacks, which show how to manipulate racy algorithms to break program integrity. Specifically, we show how to bias ML training towards attacker-specified labels, "simply" by coordinating races between threads in a malicious fashion.

We are always trying to shine a spotlight on future microarchitectural attacks, i.e., those that would occur due to microarchitecture that has been proposed but not yet implemented (as far as is publicly disclosed), or is imminently on deck to be implemented. This work started with Safecracker attacks (shorter version), which show how compressed hardware caches can be manipulated to leak (in the worst case) all of program memory. We greatly expanded this effort by opening Pandora's box, where we read the whole computer architecture literature looking for microarchitectural proposals with novel security implications. We found at least seven more classes of microarchitectural optimization that carry this dubious distinction, ranging from those that leak all of program memory (with significantly weaker assumptions than Safecracker) to those that otherwise break security-critical code in a variety of ways.

Finally, my group enjoys reverse engineering hardware for fun and profit, e.g., CPU non-inclusive cache hierarchies and uncore interconnects.

Outside of security I have been working on domain-specific acceleration. In UCNN, we highlight how weight values in deep neural networks repeat often (due to the pigeonhole principle), and design new algorithms and architectures to perform more efficient weight repetition-aware inference. SumMerge develops a more advanced weight-repetition aware inference algorithm and shows how weight repetition-aware software kernels can outperform dense kernels (e.g., Intel's MKL-DNN) on general-purpose devices. A major focus of my work in this area is to design hardware/software primitives that can be used by larger systems (e.g., accelerators) as opposed to just building out monolithic accelerators. In this direction, ExTensor proposes a new primitive called hierarchical intersection to accelerate sparse tensor algebra. In a similar vein, buffets are a new hierarchically-composable storage idiom for orchestrating data movement.

During graduate school, my research focus was how to efficiently emulate fully homomorphic encryption in hardware. This led to work ranging from taping out a secure processor to designing asymptotically better cryptography (plus a lot of other papers to improve a cryptographic primitive called ORAM). Chip bring-up was successful, and our hardware ORAM module ran at 857 MHz, dissipating 166 mW @ 1.1V in 32nm silicon. I wrote a 1-pager on the Ascend project that expounds my philosophy in secure hardware design (a bit old but philosophy is still on point).

Navigation:
  1. Peer-reviewed papers
  2. Patents
  3. Theses
  4. Misc. papers (e.g., eprints)
  5. Academic blogs
  6. Selected press
  7. Talks
  8. Posters
  9. Funding
  10. Tutorials/Misc. Resources

Peer-Reviewed Papers


Color code: Blue: conference, Green: journal, Purple: workshop.

Top architecture conferences: ASPLOS, HPCA, ISCA, MICRO
Top security conferences: CCS, NDSS, Oakland/SP, USENIX Security

  1. SumMerge: An Efficient Algorithm and Implementation for Weight Repetition-Aware DNN Inference; Rohan Prabhakar, Sachit Kuhar, Rohit Agrawal, Christopher Hughes, Christopher W. Fletcher; ICS, 2021

  2. Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture Can Leak Private Data; Jose Rodrigo Sanchez Vicarte, Pradyumna Shome, Nandeeka Nayak, Caroline Trippel, Adam Morrison, David Kohlbrenner, Christopher W. Fletcher; ISCA, 2021

  3. Leaking Secrets Through Compressed Caches; Po-An Tsai, Andres Sanchez, Christopher W. Fletcher, Daniel Sanchez; IEEE Top Picks Special Issue, 2021

  4. Lord of the Ring(s): Side Channel Attacks on the CPU On-Chip Ring Interconnect Are Practical; Riccardo Paccagnella, Licheng Luo, Christopher W. Fletcher; USENIX Security, 2021
    Artifact release coming soon

  5. Speculative Interference Attacks: Breaking Invisible Speculation Schemes; Mohammad Behnia, Prateek Sahu, Riccardo Paccagnella, Jiyong Yu, Zirui Zhao, Xiang Zou, Thomas Unterluggauer, Josep Torrellas, Carlos Rozas, Adam Morrison, Frank Mckeen, Fangfei Liu, Ron Gabor, Christopher W. Fletcher, Abhishek Basak, Alaa Alameldeen; ASPLOS, 2021
    Artifact release coming soon

  6. Jamais Vu: Thwarting Microarchitectural Replay Attacks; Dimitrios Skarlatos, Zirui Zhao, Riccardo Paccagnella, Christopher W. Fletcher, Josep Torrellas; ASPLOS, 2021
    Artifact release coming soon

  7. Streamline: A Fast, Flushless Cache Covert-Channel Attack by Enabling Asynchronous Collusion; Gururaj Saileshwar, Christopher W. Fletcher, Moinuddin Qureshi; ASPLOS, 2021
    Artifact release coming soon

  8. Mind Mappings: Enabling Efficient Algorithm-Accelerator Mapping Space Search; Kartik Hegde, Po-An Tsai, Sitao Huang, Vikas Chandra, Angshuman Parashar, Christopher W. Fletcher; ASPLOS, 2021
    Open source release coming soon

  9. Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively-Accessed Data; Jiyong Yu, Mengjia Yan, Artem Khyzha, Adam Morrison, Josep Torrellas, Christopher W. Fletcher; Communications of the ACM, Research Highlight, 2021

  10. CoTracer and RokWall: Privacy Preserving University Health Apps for COVID-19; Vikram Sharma Mailthody, Amit Agarwal, Nicholas Chen, Andrew Miller, Sanjay Patel, Edward Richter, Christopher W. Fletcher, Mohammad Behnia, Ruihao Yao, Qihao Wang, Jinjun Xiong, Lijian Wang, Leihao Chen, James Wei, Vedant Agarwal, Churan He; NDSS-CoronaDef, 2021

  11. DOVE: A Data-Oblivious Virtual Environment; Hyun Bin Lee, Tushar Jois, Christopher W. Fletcher, Carl A. Gunter; NDSS, 2021
    Open source release coming soon

  12. SparseTrain: Leveraging Dynamic Sparsity in Software for Training DNNs on General-Purpose SIMD Processors; Zhangxiaowen Gong, Houxiang Ji, Christopher W. Fletcher, Christopher J. Hughes, Josep Torrellas; PACT, 2020

  13. SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs; Zhangxiaowen Gong, Houxiang Ji, Christopher W. Fletcher, Christopher Hughes, Sara Baghsorkhi, Josep Torrellas; MICRO, 2020

  14. Speculation Invariance (InvarSpec): Faster Safe Execution Through Program Analysis; Zirui Zhao, Houxiang Ji, Mengjia Yan, Jiyong Yu, Christopher W. Fletcher, Adam Morrison, Darko Marinov, Josep Torrellas; MICRO, 2020

  15. PyTorchFI: A Runtime Perturbation Tool for DNNs; Abdulrahman Mahmoud, Neeraj Aggarwal, Alex Nobbe, Jose Rodrigo Sanchez Vicarte, Sarita Adve, Christopher W. Fletcher, Iuri Frosio, Siva Kumar Sastry Hari; DSN-DSML, 2020
    Open source release here

  16. Speculative Data-Oblivious Execution: Mobilizing Safe Prediction For Safe and Efficient Speculative Execution; Jiyong Yu, Namrata Mantri, Josep Torrellas, Adam Morrison, Christopher W. Fletcher; ISCA, 2020
    Open source release here

  17. Scalable Validation of Binary Lifters; Sandeep Dasgupta, Sushant Dinesh, Deepan Venkatesh, Vikram Adve, Christopher W. Fletcher; PLDI, 2020
    Artifact release here

  18. Feature Map Vulnerability Evaluation in CNNs; Abdulrahman Mahmoud, Siva Kumar Sastry Hari, Christopher W. Fletcher, Sarita V. Adve, Charbel Sakr, Naresh Shanbhag, Pavlo Molchanov, Michael B. Sullivan, Timothy Tsai and Stephen W. Keckler; SARA, 2020

  19. Custos: Practical Tamper-Evident Auditing of Operating Systems Using Trusted Execution; Riccardo Paccagnella, Pubali Datta, Wajih Hassan, Adam Bates, Christopher W. Fletcher, Andrew Miller, Dave Tian; NDSS, 2020
    Open source release here

  20. Creating Foundations for Secure Microarchitectures with Data-Oblivious ISA Extensions; Jiyong Yu, Lucas Hsiung, Mohamad El Hajj, Christopher W. Fletcher; IEEE Top Picks Special Issue, 2020

  21. Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data; Jiyong Yu, Mengjia Yan, Artem Khyzha, Adam Morrison, Josep Torrellas, Christopher W. Fletcher; IEEE Top Picks Special Issue, 2020

  22. MicroScope: Enabling Microarchitectural Replay Attacks; Dimitrios Skarlatos, Mengjia Yan, Bhargava Gopireddy, Read Sprabery, Josep Torrellas, Christopher W. Fletcher; IEEE Top Picks Special Issue, 2020

  23. Game of Threads: Enabling Asynchronous Poisoning Attacks; Jose Rodrigo Sanchez Vicarte, Ben Schreiber, Riccardo Paccagnella, Christopher W. Fletcher; ASPLOS, 2020
    Artifact release here

  24. Safecracker: Leaking Secrets through Compressed Caches; Po-An Tsai, Andres Sanchez, Christopher W. Fletcher, Daniel Sanchez; ASPLOS, 2020
    Artifact release here
    IEEE Micro Top Picks 2021

  25. Cache Telepathy: Leveraging Shared Resource Attacks to Learn DNN Architectures; Mengjia Yan, Christopher W. Fletcher, Josep Torrellas; USENIX Security, 2020

  26. ExTensor: An Accelerator for Sparse Tensor Algebra; Kartik Hegde, Hadi Asghari-Moghaddam, Michael Pellauer, Neal Crago, Aamer Jaleel, Edgar Solomonik, Joel Emer, Christopher W. Fletcher; MICRO, 2019
    IEEE Micro Top Picks 2020 Honorable Mention

  27. Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data; Jiyong Yu, Mengjia Yan, Artem Khyzha, Adam Morrison, Josep Torrellas, Christopher W. Fletcher; MICRO, 2019
    Formal analysis/security proof: here
    Open source release here
    Best Paper Award
    IEEE Micro Top Picks 2020
    CACM Highlight

  28. A Retrospective on Path ORAM; Emil Stefanov, Marten van Dijk, Elaine Shi, Christopher W. Fletcher, Ling Ren, Xiangyao Yu, Srinivas Devadas; IEEE TCAD, 2019

  29. Approximate Checkers; Abdulrahman Mahmoud, Paul Reckamp, Panqiu Tang, Christopher W. Fletcher, Sarita V. Adve; WAX, 2019

  30. MicroScope: Enabling Microarchitectural Replay Attacks; Dimitrios Skarlatos, Mengjia Yan, Bhargava Gopireddy, Read Sprabery, Josep Torrellas, Christopher W. Fletcher; ISCA, 2019
    Open source release here
    Highest ranked paper in double-blind review process
    IEEE Micro Top Picks 2020

  31. SecDir: Secure Directories to Defeat Directory Side Channel Attacks; Mengjia Yan, Jen-Yang Wen, Christopher W. Fletcher, Josep Torrellas; ISCA, 2019

  32. gem5-Approxilyzer: an Open Source Tool for Application-level Soft Error Analysis; Radha Venkatagiri, Khalique Ahmed, Abdulrahman Mahmoud, Sasa Misailovic, Darko Marinov, Christopher W. Fletcher, and Sarita V. Adve; DSN, 2019
    Open source release here

  33. Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration; Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal Crago, Kartik Hegde, Rangarajan Venkatesan, Stephen W. Keckler, Christopher W. Fletcher, Joel Emer; ASPLOS, 2019
    Open source release here
    IEEE Micro Top Picks 2020 Honorable Mention

  34. Minotaur: Adapting Software Testing Techniques for Hardware Errors; Abdulrahman Mahmoud, Radha Venkatagiri, Khalique Ahmed, Sasa Misailovic, Darko Marinov, Christopher W. Fletcher, Sarita V. Adve; ASPLOS, 2019

  35. Data Oblivious ISA Extensions for Side Channel-Resistant and High Performance Computing; Jiyong Yu, Lucas Hsiung, Mohamad El Hajj, Christopher W. Fletcher; NDSS, 2019
    Open source release here
    Distinguished Paper Finalist
    Finalist, CSAW Applied Research Competition 2019
    IEEE Micro Top Picks 2020

  36. Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World; Mengjia Yan, Read Sprabery, Bhargava Gopireddy, Christopher W. Fletcher, Roy Campbell, Josep Torrellas; Oakland/SP, 2019

  37. InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy; Mengjia Yan, Jiho Choi, Dimitrios Skarlatos, Adam Morrison, Christopher W. Fletcher, Josep Torrellas; MICRO, 2018
    Open source release here
    IEEE Micro Top Picks 2019 Honorable Mention

  38. Morph: Flexible Acceleration for 3D CNN-based Video Understanding; Kartik Hegde, Rohit Agrawal, Yulun Yao, Christopher W. Fletcher; MICRO, 2018

  39. UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition; Kartik Hegde, Jiyong Yu, Rohit Agrawal, Mengjia Yan, Michael Pellauer, Christopher W. Fletcher; ISCA, 2018

  40. Path ORAM: An Extremely Simple Oblivious RAM Protocol; Emil Stefanov, Marten van Dijk, Elaine Shi, T-H Hubert Chan, Christopher W. Fletcher, Ling Ren, Xiangyao Yu, Srinivas Devadas; JACM, 2018

  41. ZeroTrace: Oblivious Memory Primitives from Intel SGX; Sajin Sasy, Sergey Gorbunov, Christopher W. Fletcher; NDSS, 2018
    Open source release here

  42. Design and Implementation of the Ascend Secure Processor; Ling Ren, Christopher W. Fletcher, Albert Kwon; Marten van Dijk; Srinivas Devadas; IEEE TDSC, 2017

  43. Asymptotically tight bounds for composing ORAM with PIR; Kartik Nayak, Ling Ren, Christopher W. Fletcher, Ittai Abraham, Benny Pinkas; PKC, 2017

  44. HOP: Hardware makes Obfuscation Practical; Kartik Nayak, Christopher W. Fletcher, Ling Ren, Nishanth Chandran, Satya Lokam, Elaine Shi, Vipul Goyal; NDSS, 2017
    Open source release here

  45. Onion ORAM: A Constant Bandwidth Blowup Oblivious RAM; Srinivas Devadas, Marten van Dijk, Christopher W. Fletcher, Ling Ren, Elaine Shi, Daniel Wichs; TCC, 2016; (Alphabetical authors, L. Ren and I shared lead author)

  46. Constants Count: Practical Improvements to Oblivious RAM; Ling Ren, Christopher W. Fletcher, Albert Kwon, Emil Stefanov, Elaine Shi, Marten van Dijk, Srinivas Devadas; USENIX Security, 2015

  47. PrORAM: Dynamic Prefetcher for Oblivious RAM; Xiangyao Yu, Syed Kamran Haider, Ling Ren, Christopher W. Fletcher, Albert Kwon, Marten van Dijk, Srinivas Devadas; ISCA, 2015

  48. A Low-Latency, Low-Area Hardware Oblivious RAM Controller; Christopher W. Fletcher, Ling Ren, Albert Kwon, Marten van Dijk, Emil Stefanov, Dimitrios Serpanos, Srinivas Devadas; FCCM, 2015

  49. Freecursive ORAM: [Nearly] Free Recursion and Integrity Verification for Position-based Oblivious RAM; Christopher W. Fletcher, Ling Ren, Albert Kwon, Marten van Dijk, Srinivas Devadas; ASPLOS, 2015
    Open source release here

  50. Suppressing the Oblivious RAM Timing Channel While Making Information Leakage and Program Efficiency Trade-offs; Christopher W. Fletcher, Ling Ren, Xiangyao Yu, Marten van Dijk, Omer Khan, Srinivas Devadas; HPCA, 2014

  51. Path ORAM: An Extremely Simple Oblivious RAM Protocol; Emil Stefanov, Marten van Dijk, Elaine Shi, Christopher W. Fletcher, Ling Ren, Xiangyao Yu, Srinivas Devadas; CCS, 2013
    Best Student Paper Award
    Top Picks in Hardware & Embedded Security 2018

  52. Generalized External Interaction with Tamper-Resistant Hardware with Bounded Information Leakage; Xiangyao Yu, Christopher W. Fletcher, Ling Ren, Marten van Dijk, Srinivas Devadas; CCSW, 2013

  53. A Framework to Accelerate Sequential Programs on Homogeneous Multicores; Christopher W. Fletcher, Rachael Harding, Omer Khan, Srinivas Devadas; VLSI SoC, 2013

  54. Integrity Verification for Path Oblivious-RAM; Ling Ren, Christopher W. Fletcher, Xiangyao Yu, Marten van Dijk, Srinivas Devadas; HPEC, 2013

  55. Design Space Exploration and Optimization of Path Oblivious RAM in Secure Processors; Ling Ren, Xiangyao Yu, Christopher W. Fletcher, Marten van Dijk, Srinivas Devadas; ISCA, 2013

  56. Towards an Interpreter for Efficient Encrypted Computation; Christopher W. Fletcher, Marten van Dijk, Srinivas Devadas; CCSW, 2012

  57. A Secure Processor Architecture for Encrypted Computation on Untrusted Programs; Christopher W. Fletcher, Marten van Dijk, Srinivas Devadas; STC, 2012

  58. HORNET: a cycle-level multicore simulator; Pengju Ren, Mieszko Lis, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Nanning Zheng, Srinivas Devadas; IEEE TCAD, Vol. 31, No. 6, June 2012

  59. A Low-overhead Dynamic Optimization Framework on Multicores; Christopher W. Fletcher, Rachael Harding, Omer Khan, Srinivas Devadas; PACT (short paper), 2012

  60. Exploring Many-core Design Templates for FPGAs and ASICs; Ilia Lebedev, Christopher W. Fletcher, Shaoyi Cheng, James Martin, Austin Doupnik, Daniel Burke, Mingjie Lin, John Wawrzynek; IJRC, Article ID 439141, Volume 2012

  61. Scalable Accurate Multicore Simulation in the 1000 core era; Mieszko Lis, Pengju Ren, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Srinivas Devadas; ISPASS, 2011

  62. Brief Announcement: Distributed Shared Memory based on Computation Migration; Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Christopher W. Fletcher, Michel Kinsy, Ilia Lebedev, Omer Khan, Srinivas Devadas; SPAA (short paper), 2011

  63. Bridging the GPGPU-FPGA Efficiency Gap; Christopher W. Fletcher, Ilia Lebedev, Narges B. Asadi, Daniel R. Burke, John Wawrzynek; ISFPGA (short paper), 2011

  64. MARC: A Many-Core Approach to Reconfigurable Computing; Ilia Lebedev, Shaoyi Cheng, Austin Doupnik, James Martin, Christopher W. Fletcher, Daniel Burke, Mingjie Lin, John Wawrzynek; ReConFig, 2010

  65. ParaLearn: A Massively Parallel, Scalable System for Learning Interaction Networks on FPGAs; Narges B. Asadi, Christopher W. Fletcher, Greg Gibeling, Karen Sachs, Eric Glass, Daniel Burke, Zoey Zhou, John Wawrzynek, Wing H. Wong, Garry P. Nolan; ICS, 2010; (N. Asadi and I shared lead author)
    Best Student Paper Award

Patents


  1. Technique for secure computation; Srinivas Devadas, Christopher W. Fletcher, Marten Van Dijk; Patent No. 8909967. (Note: there is currently a bug where only Marten is listed as inventor. The lawyers are fixing it...)

Theses


  1. Oblivious RAM: From Theory to Practice; Christopher W. Fletcher; Ph.D. Thesis; [Thesis]
    George M. Sprowls Award for outstanding Ph.D. thesis in CS at MIT

  2. Ascend: An Architecture for Performing Secure Computation on Encrypted Data; Christopher W. Fletcher; S.M. Thesis; [CSG Technical Memo 508]

Other Tech Reports/Articles


  1. Speculative Taint Tracking (STT): A Formal Analysis; Jiyong Yu, Mengjia Yan, Artem Khyzha, Adam Morrison, Josep Torrellas, Christopher W. Fletcher; Technical report

  2. SparseTrain: Leveraging Dynamic Sparsity in Training DNNs on General-Purpose SIMD Processors; Zhangxiaowen Gong, Houxiang Ji, Christopher W. Fletcher, Christopher Hughes, Josep Torrellas; arXiv preprint arXiv:1911.10175

  3. Bucket ORAM: Single Online Roundtrip, Constant Bandwidth Oblivious RAM; Christopher W. Fletcher, Muhammad Naveed, Ling Ren, Elaine Shi, Emil Stefanov; Cryptology ePrint Archive (IACR), Report 2015/1065, 2015. http://eprint.iacr.org/

  4. [Author Retrospective] AEGIS: Architecture for Tamper-Evident and Tamper-Resistant Processing; G. Edward Suh, Christopher W. Fletcher, Dwaine Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas; 25 Years of the International Conference on Supercomputing, 2014.

  5. Let's Stop Trusting Software With Our Sensitive Data; Christopher W. Fletcher, Marten van Dijk, Srinivas Devadas; IEEE Design and Test of ICs, March/April 2013. The Last Byte.

Academic Blogging


  1. Approaches to System Security: Using Cryptographic Techniques to Minimize Trust; Sigarch blog [article]; with Simha Sethumadhavan.

Selected Press


  1. Cybersecurity Factory nurtures early-stage startups in a tough field; Fortune [article]

  2. The Quest to Rescue Security Research From the Ivory Tower; Wired [article]

  3. Cloud security reaches silicon; MIT News [article]

  4. Hardware Trick Could Keep Cloud Data Safe; IEEE Spectrum [article]

  5. Devadas hardware disguises cloud servers memory-access patterns thwarting timing attacks; CSAIL News [article]

  6. Protecting data in the cloud; MIT News [article]

  7. A New Type of Security Chip Guards Against Big Data Snooping; Scientific American, Ascend has been named a "World Changing Idea"! [article]

Talks (ordered by project, then time)


  1. The Rise of the Insecure Processor: What we have learned and future opportunities; IEEE SSCD Workshop keynote, 12/7/2020

  2. Principled Secure Processor Design
    1. University of Michigan, 12/05/2019
    2. Columbia University, 12/10/2019
    3. University of Wisconsin; Madison, 9/8/2020

  3. UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition; Facebook Research, 7/24/2019

  4. Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data
    1. Intel SCAP Yearly Meeting, 6/11/2019
    2. Open Source Enclaves Workshop, Berkeley CA, 7/25/2019

  5. MicroScope: Enabling Microarchitectural Replay Attacks; Intel Research Bi-Weekly SCAP Seminar Series, 5/14/2019

  6. Hardware Abstractions and Efficient Intersection for Tensor Algebra;
    1. Workshop on Compiler Techniques for Sparse Tensor Algebra, 1/26/2019
    2. DARPA SDH Open Session, 5/6/2019
    3. Facebook Research, 7/24/2019

  7. Data Oblivious Programming and Data Oblivious ISAs
    1. Open Source Enclaves Workshop, Berkeley CA, 8/29/2018
    2. International Workshop on Blockchain/Crypto Winterschool, Xi'an China, 12/10/2018
    3. Intel Research Bi-Weekly SCAP Seminar Series, 1/22/2019
    4. Intel SCAP Yearly Meeting, 6/11/2019
    [slides]

  8. Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World; AMD Weekly Seminar Series, 7/13/2018
    [slides]

  9. Systems-centric aspects in Holistic Defense against Information Leakage; Plenary talk, NSF Workshop on Side and Covert Channels in Computing Systems, Washington D.C., 3/22/2018
    [slides]

  10. Cryptography Can Outmaneuver Hardware; Hardware Security Workshop at Columbia University, New York City, 8/31/2016

  11. The Ascend Secure Processor: Concept to Silicon Implementation
    1. University of Illinois at Urbana-Champaign, 2/15/2016
    2. Stanford University, 2/23/2016
    3. Harvard University, 3/6/2016
    4. University of California--San Diego, 4/25/2016
    5. Nvidia Research, 7/14/2016

    I also gave subsets of this talk at:
    1. CHASE Conference (Conference on Secure/Trustworthy Systems and Supply Chain Assurance), University of Connecticut, 6/1/2016
    2. DIMACS Workshop (Center for Discrete Mathematics and Theoretical Computer Science), MIT, 6/11/2016

  12. Constants Count: Practical Improvements to Oblivious RAM; "ORAMorama" Technical Session at the 24th Usenix Security Symposium, Washington D.C., 8/13/2015
    [slides]

  13. Tiny ORAM: A Low-Latency, Low-Area Hardware Oblivious RAM Controller; "Implementation I" Technical Session at the 23rd IEEE Intl. Sym. on Field-Programmable Custom Computing Machines, Vancouver, Canada, 5/2/2015
    [slides]

  14. Onion ORAM: Constant Bandwidth ORAM using Additively Homomorphic Encryption;
    1. ORAM Day at Boston University, Boston, Massachusetts, 1/30/2015
    2. Charles River Crypto Day at Northeastern University, Boston, Massachusetts, 4/17/2015
    3. UBC Seminar, Vancouver, Canada, 5/3/2015
    4. ORAM Technical Session at the 13th Theory of Cryptography Conference, 1/13/2016
    [slides, shorter slides (with whole talk written out in comments section)]

  15. Hardware Security in Cloud Computing
    Presented at the Annual CSAIL Alliance Program meeting, Cambridge, 4/30/2014

  16. Suppressing the Oblivious RAM Timing Channel While Making Information Leakage and Program Efficiency Trade-offs; "Security and Cloning" Technical Session at the 20th Intl. Sym. on High Performance Computer Architecture, Orlando, Florida, 2/18/2014
    [slides]

  17. Techniques for Performing Secure Computation on Encrypted Data
    Presented at:
    1. the NSA-CSAIL visit, Cambridge, Massachusetts, 9/19/2012
    2. the MIT CSAIL security seminar series, Cambridge, Massachusetts, 10/1/2012
    3. 7th ACM Workshop on Scalable Trusted Computing (STC), Raleigh, North Carolina, 10/15/2012 (second half)
    4. 4th ACM Cloud Computing Security Workshop (CCSW), Raleigh, North Carolina, 10/19/2012 (first half)
    5. the Northrop Grumman-CSAIL visit, Cambridge, Massachusetts, 10/25/2012
    6. the Boston University security (BUSec) seminar series, Cambridge, Massachusetts, 12/10/2012
    7. MIT Lincoln Laboratory, Lexington, Massachusetts, 2/4/2013
    [slides]

  18. Bridging the GPGPU-FPGA Effciency Gap; "FPGA Architectures and Technology" Technical Session at the 19th Intl. Sym. on FPGAs, Monterey, California, 2/28/2011
    [slides]

  19. ParaLearn: A massively parallel, scalable system for learning interaction networks on FPGAs; "Applications" Technical Session at the 24th Intl. Conf. on Supercomputing, Tsukuba, Japan, 6/2/2010
    [slides]

    20. The slides for the below talks were subsumed by the ICS'10 and FPGA'11 talks:

  20. Scalable Bayesian Network Discovery with Reconfigurable Hardware
    Presented at:
    1. the BWRC Winter Retreat, Lake Tahoe, 1/10/2010
    2. the RAMP Winter Retreat, U.C. Santa Cruz, 1/28/2010

  21. Reconfigurable Computing & Bayesian Networks
    Presented at the GSRC Annual Research Symposium, San Jose, 9/3/2009

  22. Introduction to GateLib & MCMC on the BEE3
    Presented at the Nolan Lab "All Hands Meeting," Stanford, 6/15/2009

Posters


(Has not been updated since 2013.)

  1. Ascend: An Architecture for Performing Secure Computation on Encrypted Data; Presented at the ACSC Annual Conference, Boston, 11/12/2013 (and numerous other places ...)
    [poster]
    Best Poster Presentation Award, Second Place

  2. A Low-overhead Dynamic Optimization Framework on Multicores;
    Presented at:
    1. International Conference on Very Large Scale Integration, Istanbul, 10/6/2013
    2. the 21st IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques, Minneapolis, 9/20/2012
    [poster]

  3. Bridging the GPGPU-FPGA Efficiency Gap; Presented at the 19th International Symposium on Field-Programmable Gate Arrays, Monterey, 2/28/2011
    [poster]

  4. Scalable FPGA Solutions for Learning Bayesian Networks
    Presented at:
    1. the BWRC Winter Retreat, Lake Tahoe, 1/10/2010
    2. the BWRC Summer Retreat, U.C. Berkeley, 6/6/2010 (with an updated results pane)
    [poster]

  5. Curing Cancer with RCBIOS; Presented at the RAMP Summer Retreat, U. T. Austin, 6/23/2009
    [poster]

  6. flint; Presented at the RAMP Winter Retreat, U.C. Berkeley, 1/10/2009
    [poster]

Funding


* All funding amounts are my personal take/total grant budget.

  1. SRC #2020-HW-2995 (2020-2024); 70K/210K, Co PI
  2. NSF CCF #1956374 (2020-2024); 300K/1.2M, Co PI
  3. NSF CNS #1954521 (2020-2024); 300K/1.2M, Co PI
  4. NSF CNS #1942888 (2020-2025); 468K, Lead PI
  5. Google Faculty Award (2020); 26.5/53K, Lead PI
  6. NSF CNS #1909999 (2019-2022); 500K, Lead PI
  7. Intel ISRA (2018-2021); 300K/1.5M (awarded as gift), Lead PI
  8. NSF CNS #1816226 (2018-2021); 250K/500K, Lead PI
  9. DARPA SDH #HR0011-18-3-0007 (2018-2022); 466K/23M, subcontractor under NVIDIA
  10. NSF CCF #1725734 (2017-2020); 250K/500K, Co PI
  11. Too many travel grants to list...

We thank NSF, DARPA/NVIDIA, Intel and Google for their generous support!

Tutorials/Misc. Resources


  1. Crypto-hardware-software bibliography
  2. Tutorial on microarchitectural side/covert channels: ISCA'19
  3. Community blog posts:
    1. Approaches to System Security: Using Cryptographic Techniques to Minimize Trust, SIGARCH blog
    2. What’s next for processor security?, TCCA blog

© Chris Fletcher 2019