Christopher W. Fletcher

Research


I am a computer architect with special interest in security. During my Ph.D., I designed and built secure (yet high performance) hardware systems, and developed new cryptographic primitives to serve as the foundation for those systems.

Public Material


Extra Cool Stuff


Early March 2015, in a collaboration with David Wentzlaff's group at Princeton, we taped out a 25 core Ascend (aka Piton) processor in a 32nm process. Check out some layout pictures here (had to take down for legal reasons, will put it back ASAP)! The ORAM controller came out to about 1mm^2. For the final layout, we were very conservative at the top level, so the 'real' area is somewhere between .5-1mm^2.

Update (1/22/2016): We powered up the chip and tested the ORAM -- everything works! For a test harness, we have a traffic generator on the chip that simulates a last level cache miss pattern and supplies the ORAM with requests. The ORAM/chip then talks to a Spartan6 FPGA which is connected over UART to a laptop. The UART/laptop simulates a memory substrate such as DRAM. We have confirmed the design runs at 500 MHz (.9 V) so far (the design was constrained to 700 MHz at the slow process corner). See here for a chip selfie and here for a video. See here for the transcript of the first 2 accesses.

Peer-Reviewed


  1. Onion ORAM: A Constant Bandwidth Blowup Oblivious RAM; Srinivas Devadas, Marten van Dijk, Christopher W. Fletcher, Ling Ren, Elaine Shi, Daniel Wichs; TCC, 2016; (Alphabetical authors, L. Ren and I shared lead author)

  2. Constants Count: Practical Improvements to Oblivious RAM; Ling Ren, Christopher W. Fletcher, Albert Kwon, Emil Stefanov, Elaine Shi, Marten van Dijk, Srinivas Devadas; USENIX Security, 2015

  3. PrORAM: Dynamic Prefetcher for Oblivious RAM; Xiangyao Yu, Syed Kamran Haider, Ling Ren, Christopher W. Fletcher, Albert Kwon, Marten van Dijk, Srinivas Devadas; ISCA, 2015

  4. A Low-Latency, Low-Area Hardware Oblivious RAM Controller; Christopher W. Fletcher, Ling Ren, Albert Kwon, Marten van Dijk, Emil Stefanov, Dimitrios Serpanos, Srinivas Devadas; FCCM, 2015

  5. Freecursive ORAM: [Nearly] Free Recursion and Integrity Verification for Position-based Oblivious RAM; Christopher W. Fletcher, Ling Ren, Albert Kwon, Marten van Dijk, Srinivas Devadas; ASPLOS, 2015
    Open source release here

  6. Suppressing the Oblivious RAM Timing Channel While Making Information Leakage and Program Efficiency Trade-offs; Christopher W. Fletcher, Ling Ren, Xiangyao Yu, Marten van Dijk, Omer Khan, Srinivas Devadas; HPCA, 2014

  7. Path ORAM: An Extremely Simple Oblivious RAM Protocol; Emil Stefanov, Marten van Dijk, Elaine Shi, Christopher W. Fletcher, Ling Ren, Xiangyao Yu, Srinivas Devadas; CCS, 2013
    Best Student Paper Award

  8. Generalized External Interaction with Tamper-Resistant Hardware with Bounded Information Leakage; Xiangyao Yu, Christopher W. Fletcher, Ling Ren, Marten van Dijk, Srinivas Devadas; CCSW, 2013

  9. A Framework to Accelerate Sequential Programs on Homogeneous Multicores; Christopher W. Fletcher, Rachael Harding, Omer Khan, Srinivas Devadas; VLSI SoC, 2013

  10. Integrity Verification for Path Oblivious-RAM; Ling Ren, Christopher W. Fletcher, Xiangyao Yu, Marten van Dijk, Srinivas Devadas; HPEC, 2013

  11. Design Space Exploration and Optimization of Path Oblivious RAM in Secure Processors; Ling Ren, Xiangyao Yu, Christopher W. Fletcher, Marten van Dijk, Srinivas Devadas; ISCA, 2013

  12. Towards an Interpreter for Efficient Encrypted Computation; Christopher W. Fletcher, Marten van Dijk, Srinivas Devadas; CCSW, 2012

  13. A Secure Processor Architecture for Encrypted Computation on Untrusted Programs; Christopher W. Fletcher, Marten van Dijk, Srinivas Devadas; STC, 2012

  14. HORNET: a cycle-level multicore simulator; Pengju Ren, Mieszko Lis, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Nanning Zheng, Srinivas Devadas; TCAD, Vol. 31, No. 6, June 2012

  15. A Low-overhead Dynamic Optimization Framework on Multicores; Christopher W. Fletcher, Rachael Harding, Omer Khan, Srinivas Devadas; PACT (short paper), 2012

  16. Exploring Many-core Design Templates for FPGAs and ASICs; Ilia Lebedev, Christopher Fletcher, Shaoyi Cheng, James Martin, Austin Doupnik, Daniel Burke, Mingjie Lin, John Wawrzynek; IJRC, Article ID 439141, Volume 2012

  17. Scalable Accurate Multicore Simulation in the 1000 core era; Mieszko Lis, Pengju Ren, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Srinivas Devadas; ISPASS, 2011

  18. Brief Announcement: Distributed Shared Memory based on Computation Migration; Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Christopher W. Fletcher, Michel Kinsy, Ilia Lebedev, Omer Khan, Srinivas Devadas; SPAA (short paper), 2011

  19. Bridging the GPGPU-FPGA Efficiency Gap; Christopher W. Fletcher, Ilia Lebedev, Narges B. Asadi, Daniel R. Burke, John Wawrzynek; ISFPGA (short paper), 2011

  20. MARC: A Many-Core Approach to Reconfigurable Computing; Ilia Lebedev, Shaoyi Cheng, Austin Doupnik, James Martin, Christopher W. Fletcher, Daniel Burke, Mingjie Lin, John Wawrzynek; ReConFig, 2010

  21. ParaLearn: A Massively Parallel, Scalable System for Learning Interaction Networks on FPGAs; Narges B. Asadi, Christopher W. Fletcher, Greg Gibeling, Karen Sachs, Eric Glass, Daniel Burke, Zoey Zhou, John Wawrzynek, Wing H. Wong, Garry P. Nolan; ICS, 2010; (N. Asadi and I shared lead author)
    Best Student Paper Award

Patents


  1. Technique for secure computation; Srinivas Devadas, Christopher W. Fletcher, Marten Van Dijk; Patent No. 8909967. (Note: there is currently a bug where only Marten is listed as inventor. The lawyers are fixing it...)

Theses


  1. Ascend: An Architecture for Performing Secure Computation on Encrypted Data; Christopher W. Fletcher; S.M. Thesis; [CSG Technical Memo 508]

Other Tech Reports/Articles


  1. [Author Retrospective] AEGIS: Architecture for Tamper-Evident and Tamper-Resistant Processing; G. Edward Suh, Christopher W. Fletcher, Dwaine Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas; 25 Years of the International Conference on Supercomputing, 2014.

  2. Let's Stop Trusting Software With Our Sensitive Data; Christopher W. Fletcher, Marten van Dijk, Srinivas Devadas; IEEE Design and Test of ICs, March/April 2013. The Last Byte.

Selected Press


  1. Cloud security reaches silicon; MIT News [article]

  2. Hardware Trick Could Keep Cloud Data Safe; IEEE Spectrum [article]

  3. Devadas hardware disguises cloud servers memory-access patterns thwarting timing attacks; CSAIL News [article]

  4. Protecting data in the cloud; MIT News [article]

  5. A New Type of Security Chip Guards Against Big Data Snooping; Scientific American, Ascend has been named a "World Changing Idea"! [article]

Posters


  1. Ascend: An Architecture for Performing Secure Computation on Encrypted Data; Presented at the ACSC Annual Conference, Boston, 11/12/2013 (and numerous other places ...)
    [poster]
    Best Poster Presentation Award, Second Place

  2. A Low-overhead Dynamic Optimization Framework on Multicores;
    Presented at:
    1. International Conference on Very Large Scale Integration, Istanbul, 10/6/2013
    2. the 21st IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques, Minneapolis, 9/20/2012
    [poster]

  3. Bridging the GPGPU-FPGA Efficiency Gap; Presented at the 19th International Symposium on Field-Programmable Gate Arrays, Monterey, 2/28/2011
    [poster]

  4. Scalable FPGA Solutions for Learning Bayesian Networks
    Presented at:
    1. the BWRC Winter Retreat, Lake Tahoe, 1/10/2010
    2. the BWRC Summer Retreat, U.C. Berkeley, 6/6/2010 (with an updated results pane)
    [poster]

  5. Curing Cancer with RCBIOS; Presented at the RAMP Summer Retreat, U. T. Austin, 6/23/2009
    [poster]

  6. flint; Presented at the RAMP Winter Retreat, U.C. Berkeley, 1/10/2009
    [poster]

Talks (ordered by project, then time)


  1. Constants Count: Practical Improvements to Oblivious RAM; "ORAMorama" Technical Session at the 24th Usenix Security Symposium, Washington D.C., 8/13/2015
    [slides]

  2. Tiny ORAM: A Low-Latency, Low-Area Hardware Oblivious RAM Controller; "Implementation I" Technical Session at the 23rd IEEE Intl. Sym. on Field-Programmable Custom Computing Machines, Vancouver, Canada, 5/2/2015
    [slides]

  3. Onion ORAM: Constant Bandwidth ORAM using Additively Homomorphic Encryption;
    1. ORAM Day at Boston University, Boston, Massachusetts, 1/30/2015
    2. Charles River Crypto Day at Northeastern University, Boston, Massachusetts, 4/17/2015
    3. UBC Seminar, Vancouver, Canada, 5/3/2015
    4. ORAM Technical Session at the 13th Theory of Cryptography Conference, 1/13/2016
    [slides, shorter slides (with whole talk written out in comments section)]

  4. Hardware Security in Cloud Computing
    Presented at the Annual CSAIL Alliance Program meeting, Cambridge, 4/30/2014

  5. Suppressing the Oblivious RAM Timing Channel While Making Information Leakage and Program Efficiency Trade-offs; "Security and Cloning" Technical Session at the 20th Intl. Sym. on High Performance Computer Architecture, Orlando, Florida, 2/18/2014
    [slides]

  6. Techniques for Performing Secure Computation on Encrypted Data
    Presented at:
    1. the NSA-CSAIL visit, Cambridge, Massachusetts, 9/19/2012
    2. the MIT CSAIL security seminar series, Cambridge, Massachusetts, 10/1/2012
    3. 7th ACM Workshop on Scalable Trusted Computing (STC), Raleigh, North Carolina, 10/15/2012 (second half)
    4. 4th ACM Cloud Computing Security Workshop (CCSW), Raleigh, North Carolina, 10/19/2012 (first half)
    5. the Northrop Grumman-CSAIL visit, Cambridge, Massachusetts, 10/25/2012
    6. the Boston University security (BUSec) seminar series, Cambridge, Massachusetts, 12/10/2012
    7. MIT Lincoln Laboratory, Lexington, Massachusetts, 2/4/2013
    [slides]

  7. Bridging the GPGPU-FPGA Effciency Gap; "FPGA Architectures and Technology" Technical Session at the 19th Intl. Sym. on FPGAs, Monterey, California, 2/28/2011
    [slides]

  8. ParaLearn: A massively parallel, scalable system for learning interaction networks on FPGAs; "Applications" Technical Session at the 24th Intl. Conf. on Supercomputing, Tsukuba, Japan, 6/2/2010
    [slides]

  9. The slides for the below talks were subsumed by the ICS'10 and FPGA'11 talks:

  10. Scalable Bayesian Network Discovery with Reconfigurable Hardware
    Presented at:
    1. the BWRC Winter Retreat, Lake Tahoe, 1/10/2010
    2. the RAMP Winter Retreat, U.C. Santa Cruz, 1/28/2010

  11. Reconfigurable Computing & Bayesian Networks
    Presented at the GSRC Annual Research Symposium, San Jose, 9/3/2009

  12. Introduction to GateLib & MCMC on the BEE3
    Presented at the Nolan Lab "All Hands Meeting," Stanford, 6/15/2009